Senior Digital ASIC Design Engineer

Requirements

• Exposure to programming languages including C, C++, and SystemC
• Use of scripting or object-oriented programming approaches in engineering workflows
• Experience with ASIC verification.
• Pay Range:
• The annual pay range for this position is C$109,000 - C$174,000.
• #LI-BS1
• At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
• Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
• If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Benefits

Additional Information

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. Ciena's WaveLogic products are central to advancing high-performance optical networking solutions. This role contributes to the design and integration of next-generation ASIC technologies that power critical telecommunications infrastructure. The position enables delivery of scalable and high-quality silicon solutions through cross-functional collaboration. How you will make an impact: Contribute to top-level ASIC design and integration for WaveLogic products Interpret architecture and functional specifications and collaborate with systems engineers and architects Develop and assemble top-level RTL designs integrating multiple IP blocks Maintain and enhance technology-specific libraries for advanced semiconductor nodes Own and manage tool flows supporting ASIC top-level integration Create timing constraints and analyze synthesis, timing, layout, and backend reports Perform lab validation of ASIC prototypes and production silicon The must haves: Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science Experience: 5+ years of experience in ASIC design. Ability to work independently while contributing within a team environment Application of structured approaches to solving complex technical problems Written and verbal communication in English within technical environments Utilization of Verilog, SystemVerilog, and Python in digital design workflows Application of digital design concepts including synthesis, static timing analysis (STA), timing closure, and asynchronous clock domain crossing

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