Physical Design Engineer - STA

Requirements

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.
• What We Need
• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.
• What You Will Learn
• How to close timing on Tenstorrent's high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.
• Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
• Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Additional Information

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a Timing Engineer to join our silicon team. In this role, you'll drive static timing analysis and closure for complex, high-performance designs. You'll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

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