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Principal Engineer, Digital Verification Engineering

External
Analog Devices logoAnalog Devices · AZ, Chandler, East Elliot
Full-timeOn-siteToday
ClassificationClusteringPythonRoboticsTechnical WritingVerilog
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Responsibilities

  • Drive adoption of AI/ML methodologies for failure clustering, regression triage, anomaly detection, and intelligent coverage optimization
  • Define and own verification strategy, plans, and success metrics across block, top-level, and system contexts for mixed-signal ICs
  • Build and scale mixed-signal verification infrastructure including reusable SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers
  • Lead functional coverage planning, closure analysis, and sign-off for tape-out readiness
  • Drive silicon correlation by comparing simulation expectations against lab measurements, refining models and tests based on measured behavior
  • Lead verification architecture and methodology reviews, influencing best practices across projects
  • Collaborate with design, applications, and test teams to ensure verification reflects real use-cases, operating modes, and corner scenarios
  • Required Skills and Experience
  • MSEE or MSCE with 10+ years of IC verification experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
  • Expert-level proficiency in SystemVerilog and UVM with a track record of building coverage-driven verification environments for mixed-signal products
  • Track record of owning end-to-end verification readiness from planning through tape-out sign-off and production release
  • Strong Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
  • Deep knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
  • Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
  • Excellent presentation, technical writing, and communication skills

Requirements

  • Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
  • Experience with gate-level simulation, SDF back-annotation, and post-layout verification
  • Background verifying power management and interface-rich mixed-signal devices across multiple power domains
  • Strong analytical and problem-solving abilities
  • Ability to work effectively in a collaborative team environment
  • Technical Scope
  • Development and deployment of AI/ML-driven workflows for regression analytics, failure classification, and debug acceleration
  • Full verification ownership from specification analysis through coverage closure and tape-out sign-off
  • Mixed-signal verification environment architecture including analog behavioral modeling and digital-analog interface checking
  • Verification methodology definition including test plan authoring, coverage model design, and regression management
  • Collaboration and Impact
  • Champion AI/ML-driven improvements to verification workflows, sharing results and best practices across teams
  • Partner with design, applications, and test teams to translate product requirements into verification coverage that reflects real operating conditions
  • Contribute to organizational knowledge through verification reviews, methodology forums, and cross-team technical exchanges

Benefits

Health insuranceParental leave

Additional Information

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . As a Principal Design Verification Engineer, you will own verification strategy and closure for complex analog and mixed-signal ICs, from verification planning through tape-out sign-off. You will drive the adoption of AI/ML techniques to improve regression efficiency, debug throughput, and coverage closure. Your work will span multiple business units, ensuring product quality and accelerating delivery across ADI's next-generation mixed-signal and power management products.


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