High-Level Synthesis (HLS) Engineer
External
Altera · San Jose, CAPrepare for this interview
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About the role
Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to empower developers and system architects to rapidly design and deploy next-generation systems using advanced FPGA and SoC technologies. Within Altera, the High-Level Synthesis (HLS) team builds cutting-edge compiler systems that bridge the gap between software and hardware. We transform high-level programming models into highly optimized hardware implementations, enabling breakthroughs in AI, cloud infrastructure, and domain-specific acceleration. We are looking for talent who are excited to push the boundaries of compilers, systems, and hardware/software co-design.
Responsibilities
- As a member of the HLS research and engineering team, you will contribute to both production compiler systems and forward-looking research :
- Design and develop next-generation compiler infrastructure for HLS
- Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis
- Explore advanced compilation techniques for AI/ML workloads, including graph-level and system-level optimizations
- Improve end-to-end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency
- Prototype and evaluate new ideas in collaboration with research and product teams
- Contribute to publications, patents, and internal technical innovations
- Work closely with hardware architects and domain experts to co-design future acceleration platforms
Requirements
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, with 3+ years of experience
- Strong foundation in one or more of the following:
- Compiler design (e.g., optimization, IR design, code generation)
- Programming languages or systems
- Computer architecture or digital design
- Proficiency in C/C++ or similar systems programming languages
- Research experience in compilers, HLS, or hardware/software co-design
- Familiarity with LLVM, MLIR, or similar compiler infrastructures
- Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL)
- Background in optimizing AI/ML workloads or domain-specific accelerators
- Publications in relevant conferences or demonstrated research impact
- Job Type:
- Regular
- Shift:
- Shift 1 (United States of America)
- Primary Location:
- San Jose, California, United States
- Additional Locations:
- Posting Statement:
Benefits
Additional Information
Job Details: Job Description: About Altera At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry ‑ leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
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