Principal Memory Architect

Responsibilities

• Define the overall 3D-NAND memory architecture, including array organization (Plane/Bank/Page/Block structure), word line/bit line layout, shared resource strategies, etc.
• Lead architecture feasibility studies, technical risk assessments, and roadmap planning, promoting IP reuse, scalability design, and future technology node evolution.
• Design and optimize erase/read algorithms, balancing speed, endurance, data retention, and interference management (such as read disturbances and program disturbances).
• Develop ECC (Error Correction Code) strategies and integration solutions, evaluating the impact of BCH, LDPC (hardware decoding/software decoding), and other solutions on area, latency, power consumption, and error correction capabilities.
• Define page and block management level logic, supporting advanced functions such as copy-back, multi-plane operation, suspend/resume, and background erase.
• Manage the balance of performance (throughput/latency), area (die size), power consumption (active/standby power), and reliability (P/E cycles, data retention) to support product positioning (consumer/enterprise/automotive grade);
• Collaborate closely with device/process teams to optimize circuit and algorithm designs based on actual 3D stacked structures (such as CT/FG charge trapping, vertical channels, word line stacking layers);
• Participate in the selection and customization of ONFI/Toggle Mode interface protocols, defining register mappings, command set extensions, and low-power modes;
• Coordinate cross-team (circuit, device, testing, product) technical reviews, and formulate architecture design specifications and simulation verification standards;
• Support post-silicon verification, yield analysis, and customer problem-solving, optimizing architecture design in a closed-loop manner.
• Required Qualifications:
• Education: Master's degree or above (PhD preferred) in Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields.
• Other Requirements:
• 8+ years of Flash memory development experience, including at least 5 years as architecture or key technology lead;
• Proficient in 3D-NAND physical structure and operation mechanisms, with in-depth understanding of charge trapping (CT) or floating gate (FG) technologies, vertical channel, word line stacking, crosstalk, and other characteristics;
• Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling;
• Familiar with mainstream interface protocols such as ONFI 4.x / Toggle 3.0;
• Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams;
• Excellent technical documentation writing and technical decision-making communication skills;
• Ability to track cutting-edge industry technologies (such as HBM-NAND hybrid storage and in-memory computing architecture) and drive architectural innovation and patent portfolio development;
• Complete NAND architecture delivery experience, successfully mass-produced 64-layer or higher 3D-NAND products is a plus;
• In-depth understanding of the ECC architecture (BCH/LDPC) and NAND controller collaboration mechanism is preferred;
• Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture;
• Publication of NAND-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.

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Company Intel

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