SRAM QA Engineer

Requirements

• Experience - 4 to 14 Years of experience
• B.Tech/B.E/M.Tech/M.E
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Benefits

Additional Information

Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Strong knowledge and hands-on experience in QA methodologies for standard cell libraries, including test plan development, regression testing, and post-layout verification Design highly competitive circuits to meet performance/power specifications requested by customers. Guide and lead a group of engineers to deliver the SRAM IP in the given timelines. Understanding of RC network and FINFET fundamentals are necessary. Custom or Compiler SRAM/ROM development experience. Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design. Own the responsibility from SPEC to GDS and DK delivery. Review circuits, robustness reports and identify potential robustness issues. Review Layouts and suggest improvement areas to achieve competitive PPA. Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC. . Good understanding of CMOS device characteristics, design rules, and failure mechanisms (e.g., latch-up, electro-migration) to ensure design robustness. Proficiency in quality assessment of digital circuit designs, including PPA (Power, Performance, Area) optimization checks. Hands-on experience in statistical/variation analysis to validate design margins and reliability under process variations. Experience with QA automation tools for regression testing and coverage analysis.

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