RTL Design Sign Off Lead

Requirements

• BSEE required, MSEE/PHD preferred
• 8+ years of related experience
• Additional Job Description:
• Compensation and Benefits
• The annual base salary range for this position is $108,000 - $172,800 .
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Benefits

Additional Information

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be delivered to the SOC teams. In this role, you will be the technical authority responsible for defining and enforcing synchronization strategies across complex, multi-clock domains in advanced process nodes. You will own the constraint creation process for synthesis, full-chip CDC/RDC methodology, establishing rigorous constraints and waivers to ensure zero-defect silicon. You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset-glitch issues before RTL freeze. The ideal candidate has 8+ years of experience and a mastery of structural and functional verification of crossings using industry-standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian). Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical, is highly desired. As a Senior Engineer, you are expected to mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign-off for multi-site global teams.

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Company Intel

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