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Software Research Engineer/Scientist

External
Intel logoIntel · Oregon, Hillsboro
Full-timeOn-siteToday
AssemblyComplianceData AnalysisLeadershipMachine Learning
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Requirements

  • Degree in Engineering, Physical Science, Computer Science, or related fields.
  • 3+ years of experience in the semiconductor industry with emphasis on physical design and layout optimization.
  • 3+ years of experience working with process design rules or patterning modules to enable characterization and patterning viability assessment of next generation design layouts
  • External Customer Foundry Experience
  • Experience as a Physical Design Engineer or a Backend Design Engineer
  • Strong understanding of physical design layout for standard cell libraries, place and route, SRAM, or analog mixed signals
  • Some experience with development of automation flows to enable DTCO acceleration
  • Job Type:
  • Experienced Hire
  • Shift:
  • Shift 1 (United States of America)
  • Primary Location:
  • US, Oregon, Hillsboro
  • Additional Locations:
  • Business group:
  • Posting Statement:
  • Position of Trust
  • N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .Annual Salary Range for jobs which could be performed in the US: $201,580.00-284,580.00 USDWork Model for this RoleThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) complianceHealth insuranceVision insurancePaid time offEquity / stock optionsPerformance bonus

Additional Information

Job Details: Job Description: Intel is in the middle of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. Join LTD and help create the next generation of technologies that will touch the lives of people the world over for decades to come. The RET DR and Tech Def team uses current and future lithography manufacturing tools to drive Design and process Technology Co-optimization (DTCO) as well as Design For Yield (DFY) to enable advanced node definition and extend the limits of feature sizes that are patternable by Intel Foundry for semiconductor devices Responsibilities/Duties: - Must have strong problem-solving, and trouble shooting skills to apply to challenging technical problems - Engage with semiconductor design teams, fab patterning teams and design customers to develop design rules that will enable a clear path to manufacturable products on a very strict timeline - Maintain a deep understanding of VLSI physical design optimization to drive advanced node process innovation - Research, development, and implementation of Resolution Enhancement Techniques (RET) for existing and novel process technologies - Collaborate with process modules and integration teams to select operating points and develop Module Target Specs (MTS) that enable next generation layout patterns - Maintain substantial knowledge of the state-of-the-art principles and theories in lithography, optics, photoresists, computer modeling, and software engineering - Use predictive modeling, statistics, machine learning, automation capabilities and other data analysis techniques to collect, explore, and visualize fab process data that will enable rapid convergence to layouts that are manufacturable with high yield

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