Senior Staff Design Verification Engineer - Memory Sub-System (DDR/LPDDR/HBM )

Requirements

• Required Qualifications:
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
• 5-10 years of experience in ASIC/SoC verification
• Strong knowledge of DDR, LPDDR, or HBM protocols and architecture
• Expertise in System Verilog and UVM methodology
• Experience with debugging complex verification issues
• Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools)
• Solid understanding of digital design fundamentals
• Knowledge of JEDEC standards for DDR/LPDDR/HBM
• Experience with assertion-based verification (SVA)
• Exposure to performance modeling and traffic generation
• Exposure to emulation platforms (e.g., Palladium, Veloce)
• Scripting skills (Python/Perl/Shell)
• Experience with low-power verification (UPF)
• Expected Base Pay Range (USD)
• 134,390 - 201,300, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to ev

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems - spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle - sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. What You Can Expect Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3) Build and enhance UVM/System Verilog-based verification environments Develop test benches, sequences, and checkers for functional and performance validation Perform protocol-level verification for memory controllers and PHY interfaces Analyze and debug simulation failures, identify root causes, and drive resolution Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage Support emulation/FPGA validation and post-silicon bring-up (nice to have) Review design specifications and provide feedback for testability and robustness

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