Senior RTL Design Engineer
External
Synopsys · Bangalore, IndiaFull-timeOn-site4w ago
FPGAVerilog
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About the role
We are seeking an experienced, highly motivated and high-caliber individual with below expertise. Does this sound like a good role for you? Sr Staff RTL Design Engineer (R&D engineering) Location: Bengaluru Experience: 9yrs to 15yrs BSEE with 9 years of relevant experience OR MSEE with 8 years of relevant experience. Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles. Hands-on experience with Xilinx and Altera FPGA platforms, incl...
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