Digital IC Design/Verification Engineer

Requirements

• Engineering degree in electronics, computers, or software.
• Fluency with 'C', 'C++', Python and basic knowledge in Verilog, System Verilog or VHDL.
• Good knowledge of Object Oriented Programming concepts.
• Communications standards/framing structure are highly desirable (IEEE, Ethernet protocols).
• Ability to work independently as well as in teams.
• Ability to work across functions and levels.
• Preferred:
• Experience in architectural design and implementation in VLSI or FPGA is desirable.
• Basic knowledge on standard verification methods (ie UVM), regression and testplan.
• Creative design ability to solve problems demanding the highest levels of speed.
• Good English communication skills (verbal and written) is desirable
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-MFBJ

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact In Framer team, we develop and verified VLSI architecture for communication chips. We also work in IP/TopLevel integration and FW development What You Can Expect The Digital Design Engineer will be responsible for the implementation of a various Framer blocks for high-speed coherent transceiver. Responsibilities among RTL design/coding, C/C++ verification, implementing automated test cases, building, and maintaining regressions benches. Assist in writing RTL code for digital logic blocks used in PCIe systems Help create and maintain testbenches using SystemVerilog Run simulations and review waveforms to help identify and report issues Support senior engineers in preparing documentation , micro-architecture details, and design reviews Participate in verification activities such as functional testing and basic protocol checks Learn how to use debug tools, assertions, and protocol analysis methods Collaborate with design, firmware, and physical design teams to understand how different system components work together

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