Digital Design Engineer

Requirements

• 1-3 years plus experience in developing, implementing, and testing high performance communications and DSP ASIC products
• Experience mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications.
• Must be familiar with signal processing circuit structure and architecture and high performance datapath DSP circuit design and optimization.
• Must have extensive RTL experience including design, verification, and synthesis.
• Must have strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows.
• Must be familiar with reusable HDL coding styles and design for high volume manufacture
• Experience in bit-exact MATLAB and C/C++ based system simulation and evaluation a plus.
• Familiarity with DSP and PHY layer communication protocols of 802.3 is a plus.
• Expected Base Pay Range (USD)
• 97,700 - 144,410, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-JT2

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Connectivity Group What You Can Expect Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data communication networks. Develop ASIC specification, architecture, and micro-architecture of major functional blocks in complex SOC solutions Development/simulation of RTL hardware implementations in Verilog and System Verilog Document and Execute verification plan Analyze and improve design functionality with Lint, CDC and Power analysis Participate and contribute in reviews Work and communicate effectively with global team

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