Full Chip Power Integrity Engineer

Requirements

• The successful candidate's minimum qualifications will include the following:
• BS/MS in Electrical Engineering
• Circuit design experience for minimum of 2 years
• Familiar with Spice analysis
• Experience with UPF, Verdi, Redhawk, power IR/EM, physical design, and power on sequence is a plus
• Comfortable with PERL/Python, TCL, Linux Shells
• Excellent execution and strong drive to close complex design issues
• Good communication and presentation skills to enable cross functional interaction
• Job Type:
• Regular
• Shift:
• Shift 1 (Malaysia)
• Primary Location:
• Penang 15, Penang, Malaysia
• Additional Locations:
• Posting Statement:

Additional Information

Job Details: Job Description: As a key member of Global Reliability Team you will be responsible for all aspects of FPGA power intent and reliability. Responsibilities include power intent verification using UPF, power electrical rule checking, EM and IR closure, Timing derating flows, aging, and die package bump and ball intent and planning. Good cross functional collaboration needed to verify, debug, and signoff system level reliability items.

Your Match

How well this role fits your profile.

Company Intel

What employees say

Worked at altera? Share your experience