Senior Physical Design Engineer - Signoff Methodology

Responsibilities

• Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.
• Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.
• Collaborate with engineering teams to support and enhance implementation tool flows.
• Work with advanced silicon technologies and processes to deliver complex and reliable devices.
• Minimum Requirements
• 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience.
• B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field.
• Strong understanding of STA flows.
• Familiarity with PnR, physical verification (PV), and formal verification (FV).

Requirements

• Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence.
• Ability to work both independently and within a team.
• Strong self-learning skills and effective communication.
• Why Cisco?
• We are Cisco, and our power starts with you.

Additional Information

This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence.

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Company Intel

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