Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As an Analog Layout Manager with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Data Center, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.
What You Can Expect
We are seeking an experienced Analog Layout Senior Manager to lead and grow a team of analog layout engineers responsible for delivering high-quality physical layout solutions for high-speed, mixed-signal, and advanced technology integrated circuits products. This role combines technical leadership, people management, project execution, and methodology development to ensure successful delivery of complex semiconductor products across multiple technology nodes and product generations.
The ideal candidate possesses deep expertise in analog and mixed-signal layout design, strong leadership skills, and a proven track record of delivering successful tapeouts in advanced process technologies.
Team Leadership and People Management
Lead, mentor, and develop a high-performing team of analog layout engineers through technical coaching, performance management, career development, and succession planning.
Foster a culture of ownership, accountability, collaboration, innovation, and technical excellence.
Drive hiring, onboarding, retention, and growth of top engineering talent while developing future technical and organizational leaders.
Provide clear direction, motivation, and support to enable team success and continuous professional development.
Project Execution and Delivery
Own layout execution planning, resource allocation, schedule management, and quality delivery across multiple projects.
Ensure timely completion of layout milestones while maintaining high standards of quality and design integrity.
Partner with program management and engineering leadership to identify risks, establish priorities, and drive project execution.
Technical Leadership
Provide technical guidance for analog and mixed-signal layout implementation in advanced technologies, including FinFET, CMOS and BiCMOS processes.
Oversee layout development for high-speed and mixed-signal circuits.
Lead layout reviews to ensure compliance with design requirements, foundry rules, reliability standards, and industry best practices.
Drive robust implementation of matching, shielding, isolation, noise mitigation, electromigration, EM/IR, ESD protection, and manufacturability considerations.
Cross-Functional Collaboration
Collaborate closely with circuit design, physical design, CAD, verification, reliability, and program management teams throughout the product development cycle.
Support debugging, silicon bring-up activities, root-cause analysis, yield improvement initiatives, and post-tapeout issue resolution.
Facilitate effective communication and alignment across geographically distributed engineering teams.
Methodology and Continuous Improvement
Drive improvements in layout methodologies, automation, reusable IP strategies, verification flows, and overall execution efficiency.
Establish and maintain layout design standards, review processes, checklists, and best practices.
Evaluate and deploy new EDA technologies, tools, and workflow enhancements to improve efficiency and design quality.
Stay current with emerging semiconductor technologies, industry trends, and layout methodologies.
Marvell · Santa Clara, CA