Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products.
Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs through prototyping, use-case analysis, and cost/benefit trade-offs.
Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues.
Track industry trends and market needs and translate them into forward-looking roadmaps that keep NVIDIA's products ahead of the curve.
Lead debug efforts, develop workarounds, and support bringup, validation, manufacturing, and customer escalations.
What We Need to See:
BS or MS in EE/CE (or equivalent experience) with 8+ years in silicon power architecture, system-level design, validation, and power/performance optimization.
Strong EE fundamentals: digital design, low power design, DVFS, control systems, power management, timing, and architecture.
Solid understanding of firmware/driver structures and HW/SW interaction.
Familiarity with clocking, boot/reset flows, and system architecture is a plus.
Hands-on lab experience (oscilloscopes, multimeters, logic analyzers) and silicon bringup exposure are a bonus.
Programming proficiency in C/C++, Python, or Perl in Windows/Linux environments.
Strong problem-solving, collaboration, and communication skills.
Ways to Stand Out in a Crowd:
Demonstrated cross-functional leadership - experience driving alignment across architecture, silicon, firmware, and software teams on complex, ambiguous problems.
System-level intuition - the ability to reason about power and performance holistically, not just at the block level, and to translate architectural tradeoffs into clear engineering decisions.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until June 2, 2026. This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
Additional Information
NVIDIA's Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. If you want to see your work go from whiteboard to world-class silicon, this is where that happens.
Nvidia · Santa Clara, CA