Bachelor's degree in Electronics , Computer , or Telecommunications Engineering
Preferred Requirements :
Hands- on experience in digital design and RTL development
Familiarity with chip development flows and verification methodologies
Technical Knowledge:
Proficiency in C, C++, and Python
Working knowledge of Verilog , SystemVerilog , or VHDL
Solid understanding of Object-Oriented Programming principles
Ability to work both independently and collaboratively in cross-functional teams
Comfortable engaging across organizational levels and technical disciplines
Strong analytical and problem-solving skills
Languages :
English: Intermediate - Advanced
Spanish: Native or fluent
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
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Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
At Marvell Coherent DSP BU, we design cutting-edge high-performance integrated circuits that are shipped into the world's top hyper-scale and telecom networks.
You will be part of a highly skilled team involved in the design, simulation, implementation, and validation of DSP ASICs.
What You Can Expect
Analyze product specifications and architectural requirements to drive design and verification planning for high-speed communication chips
Design and develop RTL modules in Verilog / SystemVerilog alongside C++, Python, and Linux- based tooling and firmware
Prototype next-generation IP blocks to assess feasibility and de-risk future product development
Maintain and enhance silicon-proven RTL and firmware within existing Marvell product lines , ensuring functional correctness and performance
Develop and execute verification strategies including unit , integration , and regression testing using Python- based frameworks