Senior Principal Digital Design Engineer

Responsibilities

• Ownership of a sub system
• Digital circuit design and optimization (power, timing, area) including reusability
• IP evaluation and selection
• RTL coding
• Support functional simulations, give inputs for functional coverage
• SoC clock architecture
• Coverage analysis, lint and CDC analysis
• Support for backend in timing closure, develop timing constraints
• Support design for testability
• Support for power analysis
• Guide and mentor team members
• Review outputs from the design team
• HW-SW co-design and alignment with SW engineers
• Debug issues in netlist verification (0 delay, SDF simulations)
• Support for evaluation and verification of silicon
• Documentation (Datasheet, design reports)

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Company Intel

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