Sr. Verification Engineer

Responsibilities

• Responsible for planning, verification and coverage closures of RTL mainly dealing with Ethernet, SerDes interfaces, based on UVM methodology
• Identification and creation of functional coverage and following the coverage driven methodology
• Work closely with the design team and verification teams to close any assigned tasks
• Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design