Bachelor's or master's degree (BE/ B.Tech or MS/ M.Tech ) in Electronics & Communication, Electrical & Electronics Engineering, or related field from a reputed institution
4-6 years of strong experience in high ‑ speed analog, mixed ‑ signal , and custom layout design
Good understanding of electrical fundamentals and layout behavior , especially in advanced nodes
Reasonable knowledge on local device effects (LDE) and their impact on circuit performance
Expertise in device matching and symmetry, signal flow optimization, clock routing, shielding, parasitic minimization
Fair understanding of reliability aspects including EM/IR effects, latch ‑ up prevention, ESD protection, and power planning
Strong foundation in analog layout fundamentals, including matching, shielding, guard rings, and LOD/WPE effects
Good knowledge of parasitic effects and high ‑ speed layout practices
Experience with advanced technology nodes (e.g., A14,2nm,3nm,5nm ) is a plus
Proficiency in Cadence Virtuoso (Layout XL / GXL)
Familiarity with DRC/LVS tools ( Calibre , ICV, Pegasus, etc.)
Ability to handle designs across multiple abstraction levels (cell → block → macro)
Exposure to layout automation or SKILL scripting is an added advantage
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As an Analog Layout Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.
What You Can Expect
Design and implement analog layout blocks such as PLLs, ADC/DAC, LDOs, VCOs, and high ‑ speed interface circuits
Apply advanced layout techniques including device matching, symmetry, and common centroid structures
Optimize layouts for parasitics , performance, and area efficiency
Perform floorplanning , placement, and routing of complex analog/ mixed ‑ signal blocks
Ensure DRC, LVS, and ERC clean layouts and support full sign ‑ off activities
Working closely with team members to ensure alignment and successful project delivery.
Perform post ‑ layout verification , including PEX, EM/IR, and reliability analysis
Handle ECO changes and actively support tape ‑ out activities
Marvell · Bangalore, India