Expertise in full-chip & sub-hierarchy integration
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in Perl, tcl and Python
Good understanding of digital logic and computer architecture
Knowledge of Verilog
Good communication skills and self-discipline contributing in a team environment
Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Experience with multi-voltage and low-power design techniques is advantageous
Experience with Cadence Innovus is preferred
Expected Base Pay Range (USD)
132,500 - 196,140, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates a
Benefits
Health insuranceFlexible scheduleEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server and networking applications.
What You Can Expect
You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
We are hiring for multiple office locations. This is a full-time, on-site role, and employees are expected to work at their designated team location. Relocation assistance is available for qualified candidates.
Key responsibilities include:
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools
Work with RTL design teams to drive assembly and design closure.
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation
Marvell · Austin, TX