ASIC Design Engineer, Clocks

Responsibilities

• What we need to see :
• BS or (MS preferred) in EE or equivalent experience.
• 2+ years of meaningful work experience.
• Your ability to thrive in a dynamically changing environment.
• Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages.
• Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Good understanding of backend flows and requirements is a plus.
• DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable.
• Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills.
• Good team work spirit, easy to cooperate with team members.

Additional Information

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the clocking requirements for the chip, and work with backend teams to understand the physical restrictions. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

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Company Intel

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