As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
BSEE (or equivalent experience) with 15+, MSEE with 13+ years of experience or PhD with equivalent exp
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired
Extraordinary written and oral communication skills with the curiosity to work on rare challenges
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 232,000 USD - 368,000 USD. You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until June 1, 2026. This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
Additional Information
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work , to amplify human imagination and intelligence. Make the choice to join us today.
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
Nvidia · Santa Clara, CA