PCIE Design Validation Engineer

Requirements

• Skills and qualification of our IP Solution Verification and Validation Engineer are as follow:
• a. Bachelor degree in Electrical , Electronics, Computer Engineering or equivalent.
• b. Experienced in FPGA, custom IC or ASIC design and verification, demonstrated excellence in any of the product development areas from architecture, design, validation to product.
• c. Experienced using advanced system design and validation methodologies and technologies such as FPGA prototyping, emulation, simulation and co emulation.
• d. Experienced using advanced verification methodologies such as UVM, OVM, VMM, System Verilog, constrained random verification, assertion based verification, and functional coverage techniques is a strong plus.
• e. Experienced creating and executing validation plans.
• f. Experience of leading a verification or validation team is a strong plus.
• g. Familiarity or experience in RTL design with Verilog and VHDL is a strong plus.
• h. Familiarity or experience in embedded SW and HW design is a strong plus.
• i . Knowledge of PCIe is a strong plus.
• j. Familiarity with Python, Perl, TCL and shell scripts is a plus.
• k. Familiarity with Altera Quartus or Xilinx Vivado is a plus.
• l. Highly motivated to learn and adapt to fast changing technologies and environments.
• m. Exceptional analytical, problem solving and communication skills, initiative, promote innovation and teamwork.
• n. Self motivated and ability to excel in a team environment.
• o. Demonstrates fundamental values such as accountability, integrity and a winning mindset.
• Job Type:
• Regular
• Shift:
• Shift 1 (Malaysia)
• Primary Location:
• Penang 15, Penang, Malaysia
• Additional Locations:
• Posting Statement:

Additional Information

Job Details: Job Description: Job Description Altera offers a large selection of Altera lectual property IP cores optimized for Altera FPGA devices, all of which are developed for highest performance, lowest cost, ease of use and fastest time to market. The IP Solution Engineering group is responsible for High Speed Protocol IP development, which includes participating in high-level product specifications, logic( RTL) design and implementation, RTL verification, IP FPGA emulation prototyping and hardware validation using Quartus Development Kit. As an IP Solution Engineer focusing on IP Verification and Validation, you will be responsible for carrying out design validation for Altera next generation IP across the Altera FPGA IP product portfolios. The charter of IP Solution verification and validation team is to verify and validate the IP solution for robust functionality from functional simulation, FPGA emulation prototyping, hardware to complex system level environment. The verification and validation areas encompass IP protocols eg. interconnect serial protocol, ethernet base protocol and wireless communication IPs. Your specific responsibilities and career experience may include but are not limited to the following: a. Create comprehensive verification and validation plan based on FPGA IP architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives. b. Developing IP, subsystem or system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. c. Review verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics with failures debugging as well as bug filling and closure. d. Work with cross functional teams, prepare and support IP functional validation tests for IP bring-up on actual FPGA development kits using Quartus. e. Build IP FPGA emulation prototypes, creating and establishing IP subsystem (solution) validation coverage strategy and standardized framework, drive system test design implementation and overall IP system validation on HW, maximize FPGA hardware capability to bring substantial improvement to IP quality and usability for Altera FPGA IP product portfolios. f. Developing verification and validation tools and flows, as needed. g. Interfacing with 3rd party vendors for latest industry tool and methodology or VIP exposure and evaluation. h. Participate in IP roadmap planning with product marketing as well as support interface to IP customer support team. i . Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time to market. j. Provide practical, innovative solutions to complex problems. k. Participating in technical paper writing and publication.

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