Digital Design Engineer Prime (FEC)

Responsibilities

• As a digital ASIC designer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers DSP systems, and architects
• You will produce an implementation specification document and have it reviewed by your team, verification, architects, analog designers if applicable
• You are responsible for the creation and integration of new and existing RTL and/or C source code, algorithms and functions
• You are expected be able to work independently, come up with detailed design specification for an IP subcomponent and take it through all stages of design.
• You are responsible for designer testing of your code as well as debugging of your code during simulation and regression verification
• You will assist the verification team in determining coverage and provide design assertions and waivers as needed
• You are responsible for creating timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
• Report on status updates on a regular basis
• Work closely with our ASIC verification team in various stages of verification of our IP.
• Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers' technical and professional growth
• Excellent communication and interpersonal skills with demonstrated ability to convey complex technical concepts clearly and effectively influence stakeholders
• The Must Haves:
• 10+ years of ASIC/FPGA design experience successfully delivering complex designs.
• Minimum Bachelor's degree in Electrical or Computer Engineering.
• Significant experience in using C/C++, System Verilog, synthesis, power analysis, SDC, STA, CDC and simulators from major vendors.
• Experience with high level synthesis (HLS) tools and methodologies.
• Proven ability to implement designs to timing closure.
• Assets:
• Strong background in Forward Error Correction (FEC) and/or DSP.
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
• Design for low power
• Proficiency in bug tracking using Jira and source code management and revision tracking using GIT.
• Previous experience leading a team.
• Previous experience mentoring.
• Pay Range: The salary range for this role in Ottawa is $133,100 - $212,500 CAD.
• At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
• Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
• If contacted in relation to a

Benefits

Additional Information

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Senior Digital Design Engineer, you will be an integral part of a team responsible for implementing industry standard and custom subsystems for Ciena's Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects.

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