Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields.
Solid understanding of computer architecture Knowledge in micro-architecture design, RTL coding, and functional verification
Proficient using Verilog/VHDL Knowledge of design and verification tools
Experience in Perl/Python/Tcl is a plus
Must have effective interpersonal, teamwork, and communication skills
Demonstrates good analysis and problem-solving skills
Has an inherent sense of urgency and accountability
Must have the ability to multi-task in a fast paced environment
Expected Base Pay Range (USD)
151,000 - 223,440, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Ex
Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Data Center Engineering organization designs, builds, and integrates the processor, coherent cache, interconnect fabric, and the IO-bridge. The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high-performance, low-power SoCs for use in the cloud / data center and networking equipment including servers, switches, routers, secure gateways, firewall, network monitoring, and smartNICs.
What You Can Expect
Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
Take ownership of a portion of an SOC design and drive it from initial stages to completion
Collaborate on floorplan
Responsibility for interconnection of IP blocks
Static checks
Assist with subsystem and chip level verification efforts
Drive to timing closure
Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
Work closely with verification and implementation teams to meet product requirements.
Deliver micro-architectural specifications for these designs.
Utilize and participate in the development of automation tools to accelerate the pace of development.
Leverage next-generation AI tools to enhance existing work flows.
Marvell · Westborough, MA