Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies
Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process
Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization
Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams
Ideally the candidate should demonstrate:
Excellent communication and collaboration skills with ability to interface effectively with design teams, process engineers, and external customers from diverse industry segments
Requirements
Master or Ph.D. degree in Electrical Engineering, Physics, or related field with 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment
Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process Integration, Yield, and Device.
Experience in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects
Experience in scribe line layout design and process monitoring structure development
Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments
Coding/Scripting knowledge beneficial
Ability to switch between multiple projects and ability to prioritize
Required exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery
Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows
Proficiency in design rule development, validation, and waiver management processes
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, Oregon, Hillsboro
Business group:
Posting Statement:
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .Annual Salary Range forHealth insurancePaid time offEquity / stock optionsPerformance bonus
Additional Information
Job Details:
Job Description:
About MDCE Manufacturing Development and Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers. MDCE is also chartered to develop new technologies on mature node infrastructure to bring new solutions to new customers at reliable yield and performance and low cost, and this is where you are going to play a role.
Position Overview As a Collateral - Design and DFM Lead Engineer you will be at the heart of HVM and ramp of leading-edge advance logic technologies chartered with inventing and enhancing DFM methodologies for improving performance, yield and ramp across a diverse product portfolio.
Intel · California, Santa Clara