Execute and own verification activities for SerDes / AMS / mixed‑signal IPs across advanced technology nodes (5nm, 3nm, 2nm).
Develop and maintain UVM‑based testbenches , sequences, checkers, and coverage models.
Verify high‑speed interfaces such as PCIe, Ethernet, DDR, D2D, and related PHY components (PAM4/PAM2 where applicable).
Contribute to verification of calibration, link training, power modes, and firmware‑driven flows .
Debug failures across RTL, AMS models, VIPs, and testbench infrastructure .
Analyze regressions, improve stability, and drive functional, code, and coverage closure .
Collaborate closely with Design, AMS, Firmware, and Architecture teams to resolve issues and clarify intent.
Assist with GLS bring‑up, power‑aware verification, and timing‑related checks , under guidance.
Follow and contribute to verification methodologies and best practices defined by the team.
Actively learn and adopt new tools, flows, and technologies used within Central Engineering.
Requirements
Education:
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-7 years of related professional experience. or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 6 to 9 years of experience. in verification and/or AMS/mixed‑signal design environments .
Strong hands‑on experience with SystemVerilog and UVM .
Working knowledge of:
SerDes or PHY architectures
AMS / mixed‑signal concepts
Register modeling and firmware interaction
Experience integrating or using verification IPs (VIPs) .
Ability to debug issues across multiple abstraction layers with guidance.
Familiarity with regression management and coverage analysis.
Behavioral & Growth Expectations
Demonstrates strong ownership of assigned verification areas.
Executes tasks independently with attention to quality and detail .
Communicates progress, issues, and technical findings clearly to the team.
Actively seeks to deepen domain knowledge and technical breadth .
Willingness to learn from senior engineers and accept feedback.
Begins contributing beyond tasks by suggesting incremental improvements to testbenches, checks, or flows.
Nice‑to‑Have / Growth Differentiators
Exposure to AMS verification tools and modeling techniques .
Experience with link training, calibration logic, or DSP‑analog interaction .
Basic exposure to GLS, low‑power verification, or post‑silicon debug .
Interest in automation, scripting, or productivity improvements.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, includi
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Central Engineering AMS IP delivers high quality analog and mixed signal IP and verification for Marvell's advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first time right silicon, reduced integration risk, and faster time to market through strong design verification convergence and system level validation.
What You Can Expect
Marvell · Bangalore, India