Bachelor's degree in Electrical engineering, Electronics, Computer engineering, or related fields with 10-15 years of experience.
Master's degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 5-10 years of experience.
Proven experience in taping out complex SoCs and post silicon debug
Strong RTL design skills in SystemVerilog
Hands-on experience with SoC integration and debug, along with clock/reset design, CDC, and timing constraints.
Understanding of how front-end RTL decisions impact physical implementation and verification.
Familiarity with industry standard ARM protocols (Ex: APB, AHB, AXI, CHI) and SoC interconnect (NOC) architectures.
Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
Demonstrates good analytical and problem-solving skills.
Experience with scripting languages, e.g., Python or Tcl
Experience with providing technical leadership to junior engineers
Expected Base Pay Range (USD)
158,600 - 237,600, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will
Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.
What You Can Expect
Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
Take ownership of a portion of an SOC design and drive it from initial stages to completion
Collaborate on floorplan
Responsibility for interconnection of IP blocks
Static checks
Assist with subsystem and chip level verification efforts
Drive to timing closure
Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
Work closely with verification and implementation teams to meet product requirements.
Deliver micro-architectural specifications for these designs.
Utilize and participate in the development of automation tools to accelerate the pace of development.
Leverage next-generation AI tools to enhance existing work flows.
Mentor and guide junior engineers
Marvell · Santa Clara, CA