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Silicon Micro-Architect and RTL Designer

External
matx logoMatx · Mountain View, CA
$120K–$275K/yrFull-timeOn-site3w ago
Python
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Requirements

  • Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon
  • 2 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows
  • Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
  • Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals
  • Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off
  • Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off
  • Familiarity with verification, emulation platforms and methodologies is a plus
  • Hands-on experience with participation in silicon debug and bring-up is a plus
  • This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday
  • Bonus Points If You Have
  • A huge plus if you have hands-on experience with silicon and firmware implementations of PCIe, HBM, DMA, Die-to-die subsystems.

Benefits

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.Early Career - $120,000 - $275,000 + equityMid Career - $175,000 - $450,000 + equitySenior Career - $275,000 - $600,000 + equityA Stake in our success A cash/equity mix that fits your needs and option to do early exerciseHealth & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don't)Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per yearSupport to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthoodLearning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunitiesTeam Connection Team Lunches, quarterly off-sites, and regular town hallsFinancial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don't!Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expensesCommute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!MatX E[x]tras $50 per month to use on the perks you care about mostRemote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursementHealth insuranceDental insuranceVision insurance401(k)Remote work optionsFlexible scheduleEquity / stock optionsPerformance bonusParental leave

Additional Information

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results

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