M.S. in EE, Optical Engineering, Computer Engineering, or related field (strong B.S. also considered).
3+ years of relevant industry experience.
Experience writing test automation or measurement scripts that drive lab instruments (PyVISA / SCPI, or equivalent). Comfort with Git and collaborative workflows (branches, PRs).
Exposure to SerDes measurement concepts: eye / jitter, BER, equalization, link margin.
Hands-on time with lab instrumentation (scopes, BERTs, VNAs, or power meters) from coursework, internships, or research.
Coursework or project exposure to photonics, optoelectronics, or high-speed digital / SI.
Clear written communication; able to work on-site in Santa Clara, CA.
Preferred
Hands-on exposure to electro-optical validation (PICs, silicon photonics, optical transceivers, or CPO).
Familiarity with TDECQ, OMA, ER, Rx sensitivity, or DCA-based optical eye / BER measurements.
Expected Base Pay Range (USD)
108,220 - 162,100, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcri
Benefits
Health insurancePaid time offEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's Photonics Fabric group is pioneering the next generation of optical interconnect technology for AI infrastructure. The team develops cutting-edge silicon photonics and co-packaged optics solutions designed to overcome the bandwidth and power limitations of traditional electrical interconnects - enabling the massive data movement demands of large-scale AI accelerators and data center fabrics.
This posting is for the Electrical Integrated Circuits team within the group, focused on the design of high-speed optical SerDes - the analog and mixed-signal circuits at the heart of the photonics fabric. Engineers on this team work at the intersection of advanced IC design, high-speed signaling, and photonic systems, solving some of the hardest electrical-optical interface challenges in the industry.
What You Can Expect
Build and own Python automation for SerDes + PIC validation: instrument control (PyVISA / SCPI), test sequencing, calibration routines, and end-to-end measurement flows.
Develop reusable libraries and frameworks for scopes, BERTs, VNAs, tunable lasers, optical power meters, and DCAs, so the same code scales across devices, channels, and link configurations.
Support bench-level validation of SerDes Tx/Rx operating through a PIC: eye quality, jitter, equalization (CTLE / DFE / FFE), CDR, and Rx BER / link margin.
Characterize PIC devices in the live link: EAM / MZM OMA, extinction ratio (ER), TDECQ, modulator bandwidth, photodetector responsivity, and Rx sensitivity.
Help build and run integrated electro-optical test setups (probe stations, DCAs, BERTs, tunable lasers, optical power meters, fiber fixtures); assist with fiber handling and alignment.
Correlate component-level PIC data (e.g., DCA spot-checks of EAMs and PDs) with full SerDes-driven link performance.
Execute validation test plans across PVT corners and per-channel coverage
Contribute to shared validation infrastructure: version-controlled code, code reviews, and documentation.
Marvell · Santa Clara, CA