Own end-to-end manufacturing test methodology across all test stages.
Translate system specs and product POR into DFP requirements, test content, coverage, and flows.
Define and maintain the DFP roadmap, including infrastructure and turning point planning.
Partner multi-functionally to implement test content, debug hooks, and coverage improvements.
Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs.
Embed testability requirements into design to enable robust screening and debug.
Define data and analytics frameworks to support yield analysis and continuous improvement.
Lead DFP documentation as the single source of truth and feed findings into future methodologies.
What we need to see:
MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience)
6+ years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar.
Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization.
Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis.
Demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria.
Excellent communication skills and comfort authoring structured technical documents and test plans used by global manufacturing and validation teams.
Strong AI‑enabled skills and thinking - Use AI to accelerate analysis, exploration, and documentation, but also maintain rigor, originality, and judgment that do not come from AI.
Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production.
Ways to stand out from the crowd:
Integrate AI tools (LLMs, copilots, intelligent search) into daily workflows to explore architectures, test strategies, and design options.
Use AI to accelerate documentation, DFP development, and creation of scripts and data-analysis tools for optimized coverage and HVM enablement.
Apply strong engineering judgment-know when to trust AI outputs, verify against specs/data, or override them.
Build AI-assisted validation and debug workflows (e.g., log triage, anomaly detection, pattern recognition, data analysis).
Share effective methods, prompts, and tools to elevate team efficiency while maintaining technical rigor.
NVIDIA is widely considered to be one of the world's most desirable employers in the technology field. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until June 15, 2026. This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
Additional Information
The DFP Engineer - Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle.
Nvidia · Santa Clara, CA