Demonstrated experience effectively communicating in a matrix organization to achieve common goals
Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
Expertise in designing in constrained random environments using UVM, OVM, or VMM.
Experience running and debugging using HDL simulators
Demonstrated familiarity with OOP languages (C++, Java, etc.) and Proficient with OOP techniques
Demonstrated critical thinking to conceive and develop innovative solutions to solve complex engineering problems
Demonstrated leadership skills
Act independently to determine methods and procedures on new or special assignments
Must have legal authorization to work in the US. This position does not have funding to support company-sponsored immigration support.
Education:
Bachelors in EE, CE, or CS and 12+ years of related experience; or Masters degree in EE, CE, or CS and 10+ years of related experience
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400 .
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Benefits
Dental insuranceVision insurance401(k)Paid time offEquity / stock optionsPerformance bonus
Additional Information
Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements for AI and storage chips.
The engineer will be responsible for a variety of advanced verification tasks such as:
verification environment development using modern verification techniques (System Verilog and UVM)
designing verification components such as UVM agents and behavioral models
implementing coverage and assertions using System Verilog
developing random & directed test cases against the specification
This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.
Broadcom · Usa-co Broomfield