Senior Physical Design Engineer

Responsibilities

• Execute block-level physical design from synthesized netlist to GDSII: Floorplanning and power grid design
• Placement and optimization
• Clock Tree Synthesis (CTS)
• Routing and post-route optimization
• Drive timing convergence across MCMM scenarios in collaboration with STA teams
• Ensure design closure including: Setup/hold timing closure
• DRC/LVS clean signoff
• IR drop and electromigration (EM) compliance
• Debug and resolve: Congestion issues
• SI/crosstalk problems
• Functional and physical ECOs
• Collaborate cross-functionally with: RTL/design teams to improve QoR
• DFT teams for test readiness
• Packaging and full-chip integration teams
• Contribute to methodology improvements and automation through scripting
• Follow and enforce NXP design methodologies, quality and reliability standards

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Company Intel

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