Hardware Design Engineer

Responsibilities

• Define and document microarchitecture specifications for complex digital design elements for compute, memory, or networking subsystems
• Code, integrate, and debug SystemVerilog RTL designs through the chip implementation and production lifecycle
• Meet targets for Power, Performance and Area (PPA) using advanced digital design techniques for high-speed design
• Work alongside design verification and physical design team owners to converge
• Work with architects and software teams to prototype new features which improve application-level performance
• Mentor junior design engineers on high-speed digital design techniques
• Drive improvements into the design flow using AI and automation, including new EDA tool methodologies
• Required Qualifications:
• Minimum required education: Master's or PhD degree in Computer Engineering or Electrical Engineering
• Computer architecture and digital logic design
• Knowledge of AI workload acceleration techniques and industry standard interconnects and protocols (e.g. AXI, PCIe, Ethernet, HBM/DDR)
• Mastery of SystemVerilog design techniques for high speed, high performance ASICs
• Demonstrated skill in converging functionality while making design decisions trading off Power, Performance, and Area (PPA)
• Experience in digital logic synthesis tools and Static Timing Analysis (STA)
• Proficiency in using industry standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC)
• Proficiency in using tools and simulators for hardware performance analysis and tuning
• Experience implementing SystemVerilog Assertions (SVA) for checking design intent
• Familiarity with Git version control tool for managing release cycles
• Scripting skills in Python and Linux Shell
• How to Apply
• Submission Guidelines
• Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
• EEO Policy
• Benefits Summary for US-Based, Full-Time Employment Positions

Benefits

Additional Information

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale. SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets. Sambanova Hardware Design Engineers are responsible for designing component units of the Reconfigurable Dataflow Unit ASICs deployed in our AI workload acceleration systems. They work alongside architects, design verification engineers, and physical design engineers to implement innovative features in hardware which provide unique value to Sambanova.

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