Architect and define end-to-end SoC verification strategies, including simulation, emulation, and formal verification approaches, to validate complex SoC designs.
Develop and execute block, subsystem, and SoC-level verification plans, including test benches and coverage models, to ensure compliance with microarchitecture specifications.
Lead verification closure for critical interfaces, including AXI, ACE, CHI, and interconnect fabrics.
Collaborate with SoC architects, RTL designers, and firmware teams to define verification hooks, assertions, and coverage metrics.
Oversee the integration of multiple IPs such as PCIe Gen6/7, DDR5/6, and Ethernet into the SoC environment, driving verification success.
Define and promote reusable UVM-based verification methodologies and automation flows for improved team productivity.
Lead emulation and performance modeling efforts, including co-verification of digital designs with firmware and architectural simulations using advanced platforms like Palladium and Veloce.
Debug and root cause complex issues in pre-silicon environments, implementing corrective measures to ensure design functionality and performance.
Provide expert guidance and mentorship to technical leads and design verification engineers, fostering a culture of continuous learning and improvement.
Collaborate with post-silicon validation teams to incorporate learnings into future verification methodologies and infrastructure.
Requirements
Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of relevant experience;
-5+ years of people management experience
Expertise in SystemVerilog and UVM/OVM verification methodologies.
Comprehensive knowledge of SoC microarchitecture, including coherency protocols, cache subsystems, and interconnect fabrics.
Proven experience with high-speed protocols such as PCIe, DDR, AXI, CHI, or NoC.
Hands-on experience with emulation and prototyping platforms (e.g., Palladium, Veloce, FPGA-based) and formal verification tools.
Demonstrated ability to develop and maintain verification environments, including scoreboards, monitors, and VIP integration.
Masters degree in Electrical Engineering, Computer Engineering +8 years work experience or PhD + 6 years in Electrical Engineering, Computer Engineering +6 years work experience
Familiarity with power intent verification (UPF) and security verification techniques.
Experience with AI/ML accelerators, custom interconnect fabrics, or SmartNIC technologies.
Strong scripting skills (Python, Perl, or TCL) to automate verification flows and regressions.
Proven ability to drive pre-silicon to post-silicon correlation for continuous improvement.
Exceptional analytical, debugging, and technical leadership abilities, with a passion for driving innovation and excellence.
Join us and make a lasting impact on Intel's groundbreaking technologies and products.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Oregon, Hillsboro, US, Texas, Austin
Business group:
Posting Statement:
Position of Trust
This role is a Position of Trust. Should you accept th
Additional Information
Job Details:
Job Description:
The Role and Impact
We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this strategic role, you will define and implement scalable and reusable verification methodologies that ensure first-pass silicon success. As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry. This position offers a tremendous opportunity to shape the quality and performance of Intel products, ensuring they meet and exceed the expectations of customers worldwide.
Intel · California, Santa Clara