Perform physical design implementation from RTL to GDS, creating a design database ready for manufacturing.
Execute physical synthesis, floor planning, placement, routing, and clock tree synthesis using industry-standard tools such as Synopsys and Cadence.
Conduct multiple power domain analysis using standard power formats like UPF or CPF.
Carry out verification and signoff processes including formal equivalence verification, static timing analysis, reliability verification, layout verification, noise analysis, and structural design checks.
Analyze results and recommend design optimizations to address violations and enhance product architecture.
Drive performance optimization including co-optimization with process teams to deliver best-in-class designs.
Develop and improve physical design methodologies and automate design flows.
Provide technical consultation on design tradeoffs and collaborate with cross-functional teams to define pioneering design methodologies.
Provide technical leadership to team and work towards inclusive growth
Requirements
Bachelor's degree in Electronics, Computer Engineering, or a related field with 10+ years of experience; Master's degree with 8+ years of experience;
Expertise in physical design tools and methodologies, including clock tree synthesis, static timing analysis, floor planning, power and noise analysis, and RTL to GDS workflows.
Proficiency in scripting languages like Python, Perl, and TCL for automation and flow improvements.
Experience with verification and signoff processes, including equivalence verification, timing analysis, and layout verification.
Strong problem-solving skills with attention to detail and organizational capabilities.
Proven ability to collaborate effectively within teams and work in fast-paced environments.
Experience in driving tool, flow, and methodology enhancements or specific domain improvements (e.g., power, FEV, etc.).
Familiarity with defining physical design methodologies and engaging with design automation teams, vendors, and stakeholders.
Take this opportunity to make a lasting impact on Intel's innovative products and the semiconductor industry. Apply today and be part of a team that drives the future of technology.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement:
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*
Benefits
Paid time off
Additional Information
Job Details:
Job Description:
The Role and Impact
Join Intel's cutting-edge Devices Development Group as a Physical Design Engineer, where you will play a pivotal role in shaping the future of computing. In this role, you will contribute to the design and development of next-generation Client SoCs, delivering innovative solutions that push the boundaries of performance, efficiency, and reliability. You will work with leading technologies, driving Intel's mission to create world-changing technology that enriches lives across the globe. This is an exciting opportunity to collaborate with world-class teams and redefine semiconductor design, enabling breakthroughs in laptops and desktops.
Intel · Bangalore, India