Bachelor's or Masters degree in Computer Science, Electrical Engineering or related fields and 15-20 years of related professional experience
Experience with standard RTL to GDS flows and methodology
Experience with Large and complex design synthesis, Floorplanning, Place and Route, Clock tree and Timing closure of Subsystems like latest generation of PCIe, Memory, Ethernet etc.
Experience with Memory generation
Experience with leading foundries and latest process nodes 2nm, 3nm, 5nm etc
Strong scripting skills in languages such as Perl, tcl, and Python
Strong object-oriented programming skills
In-depth understanding of digital logic and computer architecture
In-depth knowledge of Verilog/VHDL
Good communication skills and self-discipline contributing in a team environment
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell Technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line.
What You Can Expect
As a Technical Manager in the Physical Design team, you will:
Architect and lead the development of next-generation physical design methodologies and automation flows
Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure
Hands on work on complex Subsystem hardening
Working with Senior and Junior engineers to deliver reference floorplan, fully synthesized, timing closed Sub System partitions to SOC team
Work with DFT team and SOC team for DFT insertion and closing timing at SOC level
Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges
Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.
Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization
Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors
Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution
Marvell · Bangalore, India