Senior Staff Design Verification Engineer

Requirements

• Minimum:
• BS in Electrical Engineering, Computer Science, or a related field with 10+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 8+ years of industry experience is preferred.
• Experience in IP/SoC verification cycle preferably from concept to tape-out to bring-up.
• Good knowledge of verification methodologies such as UVM/OVM, etc.
• Hands-on ASIC-SoC design verification tests and debug experience.
• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
• Good problem-solving skills and the passion to take on challenges (particularly in AI domain).
• Passionate about AI and thriving in a fast-paced and dynamic startup culture.
• Preferred:
• Part of Successful implementation of multiple verification environments and tape-out efforts.
• Experience with C/C++ is good
• Equal Opportunity Employment Policy

Additional Information

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bangalore offices 3 days per week. The role: Sr Staff - Design Verification Engineer

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Company Intel

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