Manager, ASIC Sustaining Engineering, Silicon Operations

Requirements

• 5+ years of technical product or program management experience
• 7+ years of working directly with engineering teams experience
• 3+ years of software development experience
• 5+ years of technical program management working directly with software engineering teams experience
• Experience managing programs across cross functional teams, building processes and coordinating release schedules
• 5+ years of project management disciplines including scope, schedule, budget, quality, along with risk and critical path management experience
• Experience managing projects across cross functional teams, building sustainable processes and coordinating release schedules
• Experience defining KPI's/SLA's used to drive multi-million dollar businesses and reporting to senior leadership
• Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
• USA, CA, Sunnyvale - 171,000.00 - 231,400.00 USD annually
• USA, WA, Bellevue - 148,700.00 - 201,200.00 USD annually

Additional Information

The ASIC Sustaining Engineer has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test. Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data. Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions. Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination. Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines. Install, qualify, and maintain in-line defect inspection and review equipment. Create and maintain specifications, process documentation, and best-known methods Key job responsibilities Lead team to identify root cause for chip performance / yield / quality issues. Analyze CP test bin / data log to identify failure mode. Electrical failure analysis and physical failure analysis to locate suspect process stage Work with appropriate supplier to define corrective actions / solutions. Trace action implementation to verify effectiveness. Product early-stage design support to help product tape-out smoothly and Si success: Design rule review & assessment for robust product design Layout review or DFM to enlarge manufacturing window Yield window characterization and device sweet spot identification for the best yield / performance process condition.

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Company Intel

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