Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications: 4-9 years of experience in formal verification
Preferred Qualifications: - BTech/MTec in Electronics, Electrical or CS
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Posting Statement:
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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Additional Information
Job Details:
Job Description:
Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
Finds and implements corrective measures to resolve failing tests.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.
Intel · Bangalore, India