Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As part of the Design Verification Team at Marvell, you will verify complex semiconductor solutions across networking, compute, storage, and infrastructure domains. These designs enable high-speed, low-latency, and power-efficient data movement for data centers, telecom and enterprise networking, including both standard and customer-specific silicon. You will ensure designs meet stringent functional and performance requirements while contributing to next-generation AI and accelerated computing architectures. This includes supporting re-architecture efforts for AI-driven workloads, validating system-level performance, and helping identify and resolve architectural bottlenecks in scalable, high-bandwidth, and energy-efficient platforms.
What You Can Expect
In this role, you will lead the verification of complex SoC and IP designs across high-performance computing, networking, and infrastructure domains by defining verification strategy, developing test plans, and driving closure using advanced UVM methodologies, including constrained-random testing, functional coverage, and assertions. You will own RTL simulation and debug activities, perform root-cause analysis of complex issues, and work closely with design and architecture teams to ensure correctness and scalability. You will also lead execution across projects by managing milestones and deliverables, while mentoring junior engineers, promoting verification best practices, and contributing to improvements in automation, regression efficiency, and overall verification infrastructure, with the ability to influence key design and architectural decisions.
- Serve as an expert in driving the architecture and development of scalable UVM-based verification environments for complex IP and SoC designs, including defining reusable frameworks, infrastructure strategy, and long-term scalability.
- Define the scope for DV, emulation, and post-silicon validation, and collaborate with stakeholders to establish timelines and ensure execution. Lead tool evaluation and drive productivity improvements through incremental and major enhancements while tracking and adopting relevant DV industry trends.
- Lead deep RTL and system-level debug efforts, performing complex root-cause analysis across design, testbench, and integration layers, and driving cross-functional resolution of critical issues impacting quality and schedules.
- Provide technical leadership across verification efforts by driving design and verification reviews, defining methodology standards, and influencing design-for-verification decisions at the architecture level.
- Lead and coordinate cross-functional execution across verification teams and stakeholders, managing risks, dependencies, and schedules while communicating status, trade-offs, and technical decisions to ensure alignment and closure.
- Apply formal verification techniques, including writing SystemVerilog Assertions (SVA) and defining formal properties, using formal tools for property and equivalence checking, and collaborating with design teams to identify corner cases, debug issues, and complement simulation-based verification.
Marvell · Westborough, MA