Guide RTL architecture and ensure robust, scalable design implementation
Lead SoC integration, chiplet/2.5D packaging alignment , and system-level optimization
Own post-silicon bring-up, debug, and root-cause analysis , ensuring production readiness
Influence industry direction and standards (e.g., JEDEC) and incorporate ecosystem trends
Requirements
Bachelor's /Masters/ PhD in Computer Science, Electrical Engineering or related fields and 15+ years of experience in semiconductor design/architecture
Proven track record of owning and delivering complex IP or SoC architecture to silicon
Deep expertise in: HBM PHY (preferred), or DDR/LPDDR/GDDR + high-speed interfaces
Microarchitecture and RTL design
System integration and silicon bring-up
Strong understanding of: High-speed interface design, training/calibration, and timing
Demonstrated ability to: Influence technical direction across teams and organizations
Lead architecture for large-scale programs
Mentor and elevate engineering teams
Preferred
Direct experience with HBM3/HBM4 and exposure to next-gen memory architecture
Background in AI/ML accelerators or hyperscale SoCs
Experience with advanced packaging (2.5D/3D, chiplets, interposers)
Engagement with standards bodies or ecosystem partners
Why This Role
Opportunity to shape next-generation memory architecture (HBM4 and beyond)
Work on cutting-edge AI and HPC platforms at scale
Influence architecture, silicon, and long-term technology roadmap
High visibility role with broad technical ownership and impact
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Central Engineering AMS-IP team provides leading-edge high speed PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
What You Can Expect
Senior Principal Logic Architect to lead the architecture and execution of next-generation HBM PHY solutions for AI, HPC, and hyperscale systems.
This is a high-impact individual contributor leadership role with end-to-end ownership across architecture, microarchitecture, and silicon delivery . The role combines deep technical expertise, system-level thinking, and cross-organizational influence to shape future memory interface technologies at scale.
Marvell · Bangalore, India