Students have to be in last year of a 5/5.5 year Engineer course at UTN-FRC/UTN-VM/UNC/IUA or doing Master/PhD in Electrical Engineer at any university of Argentina.
Intuitive and analytical understanding of transistor level and CMOS circuit design
Experience in Verilog and spice simulations
Ability to define and adhere to project schedules
Ability to have effective written and verbal communication skills
Ability to write behavioral models for both and analog and digital circuits is a plus
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
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Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's Central Engineering Team is seeking an analog mixed signal design intern to support the development of analog IP products at Córdoba (Argentina) design center. Job responsibilities include support of IC design through design and layout, silicon evaluation and characterization. The successful candidate will be self-motivated, willing to learn exciting new technologies and be able to work effectively within a talented group of individuals.
What You Can Expect
Joint design team and take advanced analog training
Training in modeling analog circuits in System Verilog (SV)
Verify SV simulations vs spice simulations
Learn testing of analog circuits using python scripts and firmware
Run co-simulation between digital and analog designs
Develop and enhance flows that support and facilitate robust analog IC design
Marvell · Cordoba, Argentina