Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 20+ years of related professional experience, OR Master's degree and/or PhD in Computer Science, Electrical Engineering, or related field with 15+ years of experience
Strong understanding of the full ASIC development process, from architecture definition through tape-out and production
Proven ability to lead and scale ASIC verification teams across global design centers
Demonstrated track record of delivering high-quality, production-grade ASICs on time
Solid understanding of SoC architecture, including processor cores, memory subsystems, and peripheral interfaces
Strong cross-functional leadership skills with the ability to influence and drive alignment across Architecture, Design, DFT, PD, FW, and System teams
Excellent communication, interpersonal, and presentation skills, with the ability to represent the DV organization to senior leadership and customers
Highly motivated, self-driven, and naturally curious about emerging technologies and verification methodologies
Good understanding of PCIe architectures and memory technologies including DDR, LPDDR, and HBM
Experience with emulation platforms and pre-silicon validation strategies
Familiarity with advanced verification techniques including formal verification, hardware-software co-verification, and post-silicon validation support
Background in high-speed interface verification including 112G+ SerDes, PCIe Gen 6/7, CXL 3.0, or custom die-to-die interconnects
Expected Base Pay Range (USD)
197,400 - 292,150, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Custom Solutions partners with the world's most advanced technology companies to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics.
What You Can Expect
Lead DV, emulation, and pre-silicon verification execution across multiple programs with a zero-defect mindset
Define DV scope, methodology, and verification strategies that scale across complex SoC programs
Architect and drive the definition and implementation of DV testbench (TB) architectures
Define execution timelines in close collaboration with stakeholders, set program goals, and take decisive action to keep execution on track
Collaborate closely with Architecture, Design, DFT, PD, FW, and System teams to ensure successful product execution from specification through tape-out
Lead tool evaluation and selection to continuously advance the DV toolset and flow
Drive continuous productivity improvements through both incremental optimizations and forklift changes to the DV flow
Monitor industry DV trends and adapt the organization to stay ahead of key developments, particularly in PCIE architectures and memory technologies (DDR, LPDDR, HBM)
Hire, build, and retain a high-performance engineering team; address ongoing training, development, and career growth needs across the organization
Marvell · Austin, TX