Experience on synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
Experience on Test structures for DFT, IP Integration, Fault models, coverage improvement techniques.
Hands-on experience on most aspects of chip-development process with proficiency in front-end design tools and methodologies.
Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
Must be a team player with a strong can-do attitude.
Effective communication and presentation skills.
Design experience in high speed (>1 GHz)/high-performance DSP products is highly desirable.
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is highly desirable.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
This role is a full-time, onsite position, requiring employees to work from the office five days per week. Candidates should be comfortable with an in-office work environment.
This role is based onsite, five days per week. Please apply only if you are able to meet this requirement
Expected Base Pay Range
54,200 - 72,200, EUR per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are n
Benefits
Flexible schedule
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem, providing low-power, high-performance solutions for cloud data center infrastructure, service providers, AI networks, enterprises, and 5G.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
You will be part of a highly-skilled, dynamic team driving the development of Marvell's next-generation high-speed PAM/Coherent DSPs and PHY designs, which utilize cutting-edge CMOS technology.
As a member of a digital design team, you will be assisting in chip design working closely with architecture team, verification team, supporting back-end teams and timing closure.
What You Can Expect
What You Can Expect
Develop overall efficient RTL using (System)Verilog, synthesis, and backend resources.
Integrate internal and external vendor IPs.
Design, debug, and support ICs, IPs and block DFT
Implement and contribute specifying chip digital features.
Work closely with the architecture, floorplanning, backend, verification, DFT, STA teams and other cross functional teams to produce high quality hardware.
Participate in various aspects of chip design RTL development, DFT design, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
Develop ASIC specification and micro-architecture of signal processing and communications algorithms.
Assist in design automation of various aspects of the CAD EDA flow.
Develop post-silicon debug and correlation.
Collaborate with cross-functional teams consisting of architects, designers, verification, physical design, and software/firmware engineers.
Marvell · Pavia, Italy