Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

About the role

We are seeking a highly skilled and experienced Timing/STA Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, STA Signoff/Margins flows & methodologies for both SOC level and block level. They should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. Additionally, experience with deep technology nodes such as 5nm/4nm would be valued. Essential Duties And Responsibilities Develop and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for sta signoff. Own and contribute to various sta related tasks like doing timing ecos for blocks and SoCs, developing custom scripts to create histograms, sta flow management, etc. Perform static timing analysis (STA) using industry-standard tools (e.g. Primetime). Define and implement timing signoff methodologies, including process corners, derates, and uncertainties. Resolve or find workarounds for tool issues, independently or working with EDA tool vendors. Conduct post-route timing checks and quality of results (QoR) analysis. Automate STA related processes/flow using scripting languages such as Tcl or Python. Create QoR dashboards, histograms for STA runs across all modes. Ensure compliance with timing signoff checklists and criteria. Document best practices and lessons learned to drive continuous improvements in future projects.