Bachelor's degree in Computer Engineering, Electrical Engineering and 6+ years of related professional experience
Master's/PhD in Computer Engineering, Electrical Engineering and 4+ years of related professional experience
Good personal communication skills and team working spirit.
Hardworking and motivated to be part of a highly competent design team.
Good communication and leadership skills to work with a global team.
Must be proficient in the following skills:
Fundamental concepts in digital logic design
Understand ASIC verification flows and methodologies
Verilog, SystemVerilog, UVM
UNIX Shell scripting (Csh, Bash)
Highly desirable skills:
Experience with VIPs
Formal verification
PCIe, UCIe protocol knowledge
Low power design
MATLAB and C/C++ based system simulation and evaluation
DSP function hardware implementation knowledge
Strong Perl and Python scripting
Expected Base Pay Range (CAD)
118,700 - 158,300, $ per annum
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.
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Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
This is an existing vacancy.
Your Team, Your Impact
Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
What You Can Expect
ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and /or chip level verification.
The responsibilities include but not limited to.
Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
Use and improve UVM DV environment
Improve the design methodology and flow.
Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
Provide the support to the product teams, for both pre and post silicon
Marvell · Toronto, Canada