Scripting: Strong scripting skills (Python, Perl, Tcl) for testbench automation.
Education: B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering.
Domain Knowledge: Expertise Mix signal Sensor IP verification.
IP test plan development.
Constraint-random test generation.
Strong debugging capabilities and RCA (Root Cause Analysis).
Ability to work on complex, Mix signal designs.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Posting Statement:
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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Additional Information
Job Details:
Job Description:
A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Key responsibilities include defining verification plans, guiding junior engineers, improving verification methodologies, ensuring coverage closure, and collaborating with architects for top-level verification.
Intel · Bangalore, India