Invent new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation.
Devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.
Explore use of LLMs (Large Language Models), GNNs (Graph Neural Networks), GANs (Generative Adversarial Networks), and Reinforcement Learning for suggesting or automatically implementing RTL modifications.
Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
What we need to see:
MS or PhD in Electrical Engineering or Computer Science or equivalent experience
3+ years of relevant experience in CAD software and VLSI hardware design
Demonstrated ability in software development with C++, particularly in algorithm development related to graph traversal, pattern matching, and optimization
Familiarity with RTL design, including Verilog and SystemVerilog code, as well as general hardware design concerns such as scan chain insertion, MBIST, clock and power distribution, and bus architectures
Familiarity with related EDA techniques, including logic synthesis, global route, static timing analysis, and SAT solvers
Strong communication and interpersonal skills
Ways to stand out from the crowd:
Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization
Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
Previous work experience including both software and hardware roles, especially involving SOC/IP integration or RTL design
Experience with various machine learning techniques for analysis, optimization, and code generation
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD. You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until June 15, 2026. This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
Additional Information
NVIDIA's success builds on a foundation of industry leading hardware. A key strategy in achieving this is our combining of the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++. We are seeking an innovative CAD Software Engineer with particular interest in strategies and algorithms for large scale RTL quality, timing, and power optimization. Such optimization usually includes a mix of graph-based algorithms, AI, and feedback from RTL designers, so having experience relevant to each of those areas would be ideal. In practice, techniques often depend on many related domains, so a solid understanding of DFT, clock distribution, power gating, and other SOC integration aspects is essential.
Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it!
Nvidia · Santa Clara, CA